The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. It performs down conversion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion.
The HSP50214B Programmable Downconverter (PDC) is a digital tuner that down‑converts sampled IF signals to baseband digital samples. It provides LO generation, decimation, programmable FIR filtering, resampling, AGC, frequency discrimination and multi‑chip synchronization, and interfaces directly with a DSP microprocessor.
Key features include up to 65 MSPS front‑end processing, 55 MHz back‑end processing, a decimation factor from 4 to 16384, and up to 255‑tap programmable FIR filters. The device supports multiple clock inputs (CLKIN, PROCCLK, optional REFCLK) and offers two parallel output modes (Direct Output Port and Buffer RAM Output Port).
| Front‑End Processing Rate | Up to 65 MSPS (CLKIN) |
|---|---|
| Back‑End Processing Rate | Up to 55 MHz (PROCCLK) |
| Overall Decimation Factor | 4 to 16384 |
| Maximum Output Sample Rate | 12.94 MSPS |
| Maximum Output Bandwidth | 982 kHz low‑pass |
| Programmable FIR Tap Count | Up to 255 taps |
| Package Type | 120 Ld MQFP (Q120.28×28) |
The HSP50214B has three clock inputs; two are required and one is optional.
Two parallel output modes are available: a Direct Output Port and a Buffer RAM Output Port.
The device supports up to 65 MSPS front‑end processing rates (CLKIN).
It is offered in a 120 Ld MQFP (Q120.28×28) and a Pb‑free 120 Ld MOFP package.