The HSP50016 is a high performance digital down converter that performs down conversion, filtering and decimation on sampled data streams of up to 16 bits in width and up to a 75 MSPS data rate.
This datasheet describes the Intersil HSP50016 Digital Down Converter (DDC), a single‑chip synthesizer, quadrature mixer and low‑pass filter capable of handling up to 75 MSPS 16‑bit input data. It outlines the internal architecture, including the mixer, high‑decimation filter, FIR filter, phase generator and output formatter.
The document provides key features, application examples, pin configurations for the 44‑lead PLCC package, timing diagrams, and detailed specifications such as input data rate, spurious‑free dynamic range, and decimation factors.
| Maximum Input Data Rate | 75 MSPS |
|---|---|
| Data Input Width | 16‑bit |
| Frequency Selectivity | <0.006 Hz |
| Passband Ripple | <0.04 dB |
| Stopband Attenuation | >104 dB |
| Filter Shape Factor | <1.5 |
| Decimation Factors | 32 to 131,072 |
| Test Access Port Standard | IEEE 1149.1 |
| Package Type | 44‑lead PLCC |
The chip supports up to 75 MSPS input data rate.
It is available in a 44‑lead PLCC package.
Yes, it includes an IEEE 1149.1 test access port.