This document introduces the Atmel XMEGA clock system, including internal and external oscillators, crystal oscillator failure monitor, high frequency phase locked loop and clock prescalers.
The manual provides an overview of the Atmel XMEGA clock system, describing the various internal and external clock sources, the internal PLL multiplier, and the digital frequency‑locked loop (DFLL) used for automatic runtime calibration. It also details the real‑time counter (RTC) and the external clock‑source failure monitor.
Four hands‑on tasks guide the reader through changing the system clock, using the internal PLL, enabling runtime calibration, and configuring the RTC, with step‑by‑step instructions for building and debugging example projects in Atmel AVR Studio.
| Internal 2 MHz oscillator (factory‑calibrated) | 2 MHz |
|---|---|
| Internal 32 MHz oscillator (factory‑calibrated) | 32 MHz |
| Ultra‑low‑power 32 kHz RC oscillator | 32 kHz |
| PLL multiplication factor | 1× to 31× |
The XMEGA starts up running from an internal 2 MHz factory‑calibrated source.
There are five internal clock sources, including the internal PLL.
All internal sources except the ultra‑low‑power 32 kHz RC oscillator can be used as the main system clock.
When enabled, the DFLL compares the oscillator frequency with a reference clock and adjusts the calibration register by one step to correct the frequency.