Industrial

This document describes a 4-bit magnitude comparator that can be used to compare straight binary or BCD codes. It features high expandability, low power dissipation, and short delay times.

The MM74HC164 is an 8-bit serial-in/parallel-out shift register that utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits, while offering speeds comparable to low power Schottky devices. This shift register has gated serial inputs and a CLEAR function. Each register bit is a D-type master/slave flip-flop. Inputs A and B provide complete control over the incoming data. A LOW level at either or both inputs inhibits the entry of new data and resets the first flip-flop to a low level at the next clock pulse. A high level on one input enables the other input to determine the state of the first flip-flop. Data at the serial inputs can be changed while the clock is HIGH or LOW, but only data that meets the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive-going transition of the clock pulse. The CLEAR function is independent of the clock and is accomplished by a low level at the CLEAR input. The 74HC logic family is functionally and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

This document describes a dual J-K flip-flop with preset and clear functions, named TLF5074 MM54HC76 MM74HC76. It utilizes advanced silicon-gate CMOS technology to achieve low power consumption, high noise immunity, and the ability to drive 10 LS-TTL loads.

5476 is a dual master-slave J-K flip-flop with complementary outputs produced by National Semiconductor. It has two independent positive pulse triggers, which process J and K data after a complete clock pulse. When the clock is low, the slave is isolated from the master. When the clock is positive, the data from the J and K inputs is transferred to the master. When the clock is high, the J and K inputs are disabled. When the clock is negative, the data from the master is transferred to the slave. The logic state of J and K inputs must not be allowed to change while the clock is high. The data is transferred to the outputs on the falling edge of the clock pulse. When setting or resetting the outputs, a low logic level on the preset or clear inputs will be independent of the logic levels of the other inputs.

This document describes the features and characteristics of the DM7476 dual master-slave J-K flip-flops with clear, preset, and complementary outputs, produced by Fairchild Semiconductor Corporation.

The MI-ComPAC is a complete single, dual, or triple output DC-DC power supply that delivers up to 300W from inputs of 28Vdc or 270Vdc. The MI-ComPAC meets the conducted emissions and conducted susceptibility specifications of MIL-STD-461C/D/E and offers complete input transient, surge, and spike protection to the most severe levels of MIL-STD-1275A, 704A. Reverse polarity protection and over/undervoltage lockout provide additional safeguards against potentially damaging line conditions. The MI-ComPAC also features a master disable.

5474/DM5474/DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset/Clear and Complementary Outputs

The DM7474 is a dual positive-edge-triggered D-type flip-flop with preset, clear, and complementary outputs. It contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. The document also provides a connection diagram and a function table.

Micrel MIC5156/5157/5158 Super LDO™ Regulator Controller is a single IC solution for high-current low-dropout linear voltage regulation. Super LDO™ Regulators have the advantages of an external component count, programmable output voltage, and low static current.

dm7473 is dual master-slave j-k flip-flops with clear and complementary outputs

This document introduces C2 Compact Flash© Card Connectors MI20/21 Series. The series features compact design, ground terminals, card ejection mechanism and suitable for PDA, digital still cameras etc.

Mitel MH88435 Data Access Arrangement (D.A.A.) is a data access device that provides a complete interface between audio or data transmission equipment and a telephone line. All functions are integrated into a single thick film hybrid module that provides high voltage isolation, very high reliability and optimum circuit design, requiring a minimum of external components.

MGFC5211 is a GaAs MMIC chip produced by Mitsubishi Electric. It is specially designed for 21.2~23.6GHz band High Power Amplifier (HPA). Its maximum working frequency is 21.2~23.6GHz, linear gain is greater than 13dB, and output power is greater than 23dBm.

This document describes the features and characteristics of TL6518 DM7446A DM5447A DM7447A BCD to 7-segment decoders/drivers, including circuits with active-low outputs, full ripple-blanking input/output controls, lamp test input, automatic leading and trailing zero-blanking control, etc. The products have features such as lamp intensity modulation capability, open-collector outputs for driving indicators directly, lamp test provision, leading-trailing zero suppression, etc.

This document describes the features and characteristics of TL6517 DM5445 DM7445 BCD-to-decimal decoders-drivers. It consists of eight inverters and ten four-input NAND gates, which are used to decode BCD input data into outputs. Full decoding of BCD input logic ensures that all outputs remain off for all invalid (10-15) binary input conditions. These decoders feature high-performance NPN output transistors designed for use as indicator-relay drivers or as open-collector logic-circuit drivers. The high-breakdown output transistors are compatible for interfacing with most MOS integrated circuits.