This document describes a dual J-K flip-flop with preset and clear functions, named TLF5074 MM54HC76 MM74HC76. It utilizes advanced silicon-gate CMOS technology to achieve low power consumption, high noise immunity, and the ability to drive 10 LS-TTL loads.
This document is a datasheet for the MM54HC76 and MM74HC76 dual J-K flip-flops. These high-speed devices utilize advanced silicon-gate CMOS technology to achieve low power consumption and high noise immunity while driving 10 LS-TTL loads. They are functionally and pin-out compatible with the standard 54LS/74LS logic family.
| Typical propagation delay | 16 ns |
|---|---|
| Low input current | 1 pA maximum |
| Low quiescent current | 40 µA maximum |
| High output drive | 10 LS-TTL loads |
| Maximum Operating Frequency | 30 MHz |
| Supply Voltage Range | 2 to 6 V |
Yes, they are functionally and pin-out compatible with the standard 54LS/74LS logic family.
The device has the ability to drive 10 LS-TTL loads.
The typical propagation delay is 16 ns.