Motorola MC10ELT21/MC100ELT21 Differential PECL to TTL Translator Datasheet

This document is about the technical data of MC10ELT/100ELT21


Motorola MC10ELT21/MC100ELT21 Differential PECL to TTL Translator Datasheet - cover page
Brand
Motorola
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
4
File format
PDF
File size
56 KB
Published
10 July, 2012
Updated
30 September, 2023
MD5 checksum
F04DE96B42B6C364D0B142B45F5A4081

About this manual

The MC10ELT21 and MC100ELT21 are differential PECL to TTL translators designed for applications requiring space, performance, and low power. The device utilizes the MOSAIC 1.5 process and is available in an 8-lead SOIC package. It supports both positive MECL 10H and positive ECL 100K logic levels.

What's inside

  • Description
  • Pin Description
  • Maximum Ratings
  • TTL Output DC Characteristics
  • PECL Input DC Characteristics
  • AC Characteristics
  • Outline Dimensions

Specifications

Typical Propagation Delay3.5ns
TTL Output Current24mA
Package TypeSmall Outline SOIC
Operating Temperature Range-40 to 85 °C
Storage Temperature Range-55 to +150 °C
DC Supply Voltage (Max)7.0 V

Frequently asked questions

What logic standards is the MC10ELT21 compatible with?

The MC10ELT21 is compatible with positive MECL 10H logic levels, while the MC100ELT21 is compatible with positive ECL 100K logic levels.

What is the recommended bypass capacitor for the VBB pin?

The VBB pin should be bypassed to ground via a 0.01uF capacitor.

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