MC10EL/100EL35 is a high-speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. It features a 525ps propagation delay, 2.2GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors, and >1000V ESD protection.
This datasheet describes the MG 10EL/100EL35 (MC10EL35/MC100EL35), a high-speed JK flip-flop designed for semiconductor applications. The device features asynchronous reset activation with logic HIGH and operates using negative clock edges to transfer data from the master portion to the slave.
| Toggle Frequency (Typ) | 2.2GHz |
|---|---|
| Propagation Delay (Max, -40°C) | 745 ps |
| Setup Time J,K (Typ) | 150 ps |
| Hold Time J,K (Typ) | 250 ps |
| Package Type | D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05 |
The reset pin is asynchronous and is activated with a logic HIGH.
Data enters when the clock signal is LOW.