User guide for Altera's RapidIO MegaCore Function IP core, covering parameter settings, functional description, and integration for FPGA designs.
This document provides detailed instructions for using the RapidIO MegaCore Function IP core in Altera FPGAs. It covers parameter settings, functional descriptions, signal interfaces, and testbench configurations. The guide is targeted at designers integrating RapidIO into high-performance computing and I/O applications.
The document includes chapters on installation, simulation, hardware testing, and specific device family support, including Arria 10. It also details register settings, clocking, reset behavior, and error management for the RapidIO protocol.
It is a high-performance MegaCore function that targets high-performance, multicomputing, high-bandwidth, and coprocessing I/O applications.
The interconnect is designed to pass data and control information between microprocessors, digital signal processors, communications and network processors, system memories, and peripheral devices.