This user guide provides instructions for configuring, simulating, and integrating the Altera RapidIO II MegaCore Function IP core for FPGA designs.
The Altera RapidIO II MegaCore Function is an IP core that complies with the RapidIO v2.2 specification. It is designed for high-performance, multi-computing, and high-bandwidth applications, facilitating data and control information transfer between microprocessors, DSPs, and peripheral devices within an FPGA system.
This document details the features, parameter settings, and functional descriptions of the IP core. It covers installation, simulation using ModelSim and VCS, integration into Qsys designs, and the specific configuration of physical, transport, and logical layers. Additionally, it provides information on interfaces, signals, software memory maps, and testbench usage.
| Specification Compliance | RapidIO v2.2 specification |
|---|---|
| Target Applications | high-performance, multi-computing, high-bandwidth, and co-processing I/O applications |
| Document Version | v15.0 |
| Publication Date | July 2015 |
It complies with the RapidIO v2.2 specification.
It targets microprocessors, digital signal processors (DSPs), communications and network processors, system memories, and peripheral devices.