Altera DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide

About this manual

This document serves as a user guide for Altera's DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP. It provides comprehensive information on the features, parameter settings, functional descriptions, and design flow for these MegaCore functions. The guide supports both full-rate and half-rate DDR and DDR2 SDRAM interfaces.

What's inside

• About This IP Release Information
• Getting Started Design Flow
• Parameter Settings
• Compile and Simulate
• Functional Description—ALTMEMPHY
• Functional Description—High-Performance Controller
• Functional Description—High-Performance Controller II
• Latency
• Timing Diagrams

Specifications

Frequently asked questions

What are the two controller architectures available?

The two controller architectures are high-performance controller (HPC) and high-performance controller II (HPC II).

What does the ALTMEMPHY megafunction do?

The ALTMEMPHY megafunction is an interface between a memory controller and the memory devices, and performs read and write operations to the memory.