This document describes the transceiver architecture, clocking, and channel binding for Altera Cyclone V devices supporting protocols like PCIe and CPRI.
This document provides an overview of the transceiver architecture in Altera's Cyclone V devices. It details the structure of transceiver channels, clock networks, and support for various high-speed protocols such as PCI Express (PCIe) and Common Public Radio Interface (CPRI). The text notes that this specific version is no longer being maintained and refers users to the English version on Intel's website for updates.
| Data Rate (Minimum Power) | 3.125Gbps and 6.144Gbps |
|---|---|
| PCIe Support | Base Specification 2.0 Gen1 and Gen2 up to x4 bonded channels |
| Transceiver Channels Count | Up to 12 serial data rates between 614Mbps and 6.144Gbps |
| Transceiver Bank Composition | 3 channels per bank |
The devices support a wide range of protocol and data rate standards, including PCI Express (PCIe) Base Specification 2.0 Gen1/Gen2 and Common Public Radio Interface (CPRI).
Cyclone V devices have up to 12 serial data rate transceiver channels operating between 614Mbps and 6.144Gbps.
Each transceiver bank consists of three channels, and devices can have up to four banks named GXB_L0 through GXB_L3.