A comprehensive guide compiling user experiences, reviews, and design documents for Altera Cyclone V SoC FPGA development across multiple hardware platforms.
This document is a compilation of learning notes, reviews, and design documents generated by EEworld community members during an Altera SoC deep experience activity. It serves as a reference for beginners and advanced users interested in SoC FPGA development.
The content is organized into four main sections, each focusing on a specific hardware platform: TerAsic DE1-SoC board, Embest SoC board (Lark), Arrow SoC Kit, and Macnica Helio Kit. The articles progress from basic introductions and environment setup to advanced topics like Linux integration, OpenCL usage, and specific application designs such as face detection and high-speed data acquisition. This manual is written in Chinese.
| Processor Core | Dual-core ARM Cortex-A9 |
|---|---|
| Programmable Logic | 85K Programmable Logic Elements |
| Memory (FPGA) | 64MB SDRAM |
| Memory (HPS) | 1GB DDR3 SDRAM |
| Network Interface | 10/100/1000 Ethernet |
| USB Interfaces | Two Port USB 2.0 Host |
The guide covers four specific hardware platforms: TerAsic DE1-SoC board, Embest SoC board, Arrow SoC Kit, and Macnica Helio Kit.
The main advantage is the high-speed interconnection between the processor and FPGA, which offers more design choices and flexibility.
Version 13.1 of SoCEDS is recommended for 32-bit systems, as newer versions only support 64-bit systems.