This document describes the NLSF1174 model, which consists of six D flip-flops with common clock and reset inputs. Each flip-flop is loaded with a low-to-high transition of the clock input. Reset is asynchronous and active low. All inputs/outputs are standard CMOS compatible.
The document describes the NLSF1174, a device consisting of six D flip-flops with common Clock and Reset inputs. Each flip-flop triggers on a low-to-high transition of the clock input, while the reset function is asynchronous and active low. All inputs and outputs are standard CMOS compatible.
| Number of Flip-Flops | Six |
|---|---|
| Operating Voltage Range | 2.0 to 6.0 V |
| Output Drive Compatibility | 10 LSTTL Loads |
| Chip Complexity | 162 FET |
The Reset is asynchronous and active low.
Yes, all inputs/outputs are standard CMOS compatible.