Altera Cyclone V Hard IP for PCI Express User Guide

About this manual

This document serves as a user guide for the Cyclone V Hard IP for PCI Express megafunction, providing instructions for design engineers using the Altera Complete Design Suite. It details the usage of the MegaWizard Plug-In Manager and Qsys Design Flows to create and customize the IP core for both Endpoint and Root Port configurations.

The guide covers system settings, IP core architecture, interface descriptions (Avalon-ST, Avalon-MM, and Physical Layer), register definitions, and protocol details. It also includes sections on debugging hardware bring-up issues, optional features like ECRC, and provides design examples with testbench procedures.

What's inside

• Datasheet Features
• Getting Started with MegaWizard Plug-In Manager
• Getting Started with Avalon-MM IP Core
• Parameter Settings
• IP Core Architecture
• IP Core Interfaces
• Register Descriptions
• Reset and Clocks
• Transaction Layer Protocol
• Debugging Hardware Bring-Up Issues

Frequently asked questions

When was this document published?

The document publication date is June 12, 2012.

Which design flows are covered in this manual?

The manual covers the MegaWizard Plug-In Manager Design Flow and the Qsys Design Flow.