This document provides a guide on implementing Configuration via Protocol (CvP) in Altera FPGAs. It provides detailed information on CvP implementation, including how the configuration protocol works and the format of configuration files.
This user guide describes the features and implementations of the Configuration via Protocol (CvP) scheme in supported Altera FPGA families. It focuses on how to use the CvP scheme in supported FPGAs and does not explain the PCI Express (PCIe) protocol itself. The guide primarily uses the Stratix V device in illustrations, guidelines, and examples, though information specific to other device families is stated accordingly.
The CvP scheme utilizes the autonomous PCIe hard IP block feature to allow the FPGA to meet PCIe power-up timing specifications. By making the embedded PCIe core operational before the FPGA fabric is configured, it offers benefits such as reduced cost, design protection against unauthorized tampering, and the ability to update the FPGA fabric image without system downtime or full chip reinitialization.
| Supported Device Families | Arria V, Cyclone V, and Stratix V |
|---|---|
| Document Version | 1.1 |
| Publication Date | January 2012 |
The benefits include reduced cost by storing fabric configuration data in host memory, design protection against unauthorized tampering, and the ability to update the FPGA fabric without system downtime.
The CvP scheme is supported in Arria V, Cyclone V, and Stratix V devices.
No, you cannot use the embedded PCIe hard IP block as a root complex when it is configured for CvP.