This application note provides information about how to configure the general purpose timers (GPTs) integrated in the SPEAr600 embedded MPU family.
The document details the architecture of the five GPT blocks within the SPEAr600 subsystem, describing their independent 16-bit counter channels and selectable clock sources. It explains how to configure the READ_Clk (APB clock) and CNT_Clk inputs using specific register addresses.
A significant portion of the guide addresses timing issues when reading free-running counters with asynchronous or non-phase-aligned clocks. It provides workarounds for scenarios where the counter clock is much slower than the read clock, such as generating system ticks in an operating system.
| Counter width per channel | 16-bit counter register |
|---|---|
| Number of GPT blocks | Five different GPT blocks |
Set bit 11 of the PRPH_CLK_CFG register (0xFCA8_0028) for GPT4, or bit 12 for GPT5.
Read the counter three times consecutively and discard the unstable value to ensure accuracy.