This Engineer-to-Engineer Note (EE-179) provides specific hardware design guidelines for systems incorporating ADSP-TS20xS TigerSHARC processors, including the ADSP-TS201S, ADSP-TS202S, and ADSP-TS203S. The document focuses on silicon revisions 1.0 and higher and addresses critical hardware issues to ensure reliable system operation.
The guide details the four power supply domains: VDD (Internal), VDD_A (Analog PLL), VDD_IO (External I/O), and VDD_DRAM (DRAM). It outlines specific requirements for bypass capacitors, inductors, and filtering circuits for each domain, emphasizing the priority of VDD_A decoupling to ensure a clean power supply for the clock generator PLLs. Additionally, it covers the configuration of VREF and SCLK_VREF pins and the handling of No-Connect (NC) pins.
| Supported Processor Models | ADSP-TS201S, ADSP-TS202S, and ADSP-TS203S |
|---|---|
| Silicon Revision Requirement | 1.0 and higher |
| Recommended VDD Bulk Capacitance | Minimum of 470 µF |
| Recommended VDD_DRAM Bulk Capacitance | Minimum of 47 µF |
| Recommended VDD_IO Bulk Capacitance | Minimum of 100 µF |
The processor has four power supply domains: VDD (Internal), VDD_A (Analog PLL), VDD_IO (External I/O), and VDD_DRAM (DRAM).
There are no specific power sequencing requirements other than the VDD_DRAM voltage must occur last.