This Engineer-to-Engineer Note (EE-241) provides a step-by-step guide for porting source code from first and second generation SHARC DSPs (ADSP-2106x and ADSP-2116x) to the TigerSHARC processor family. It addresses architectural differences, including register files, data addressing, program sequencers, DMA, and C run-time environments.
| Core Clock Rate (SHARC ADSP-2106x) | 40-66 MHz |
|---|---|
| Register File Size (SHARC ADSP-2106x) | 32x40 bits |
| Multiprocessor Support (SHARC) | up to six SHARC processors |
It is a step-by-step guide for porting SHARC code to its TigerSHARC equivalent.
The first and second generation ADSP-2106x and ADSP-2116x SHARC DSPs.
The ADSP-TS101 and ADSP-TS20x TigerSHARC processors.
Yes, multiple code examples are provided to help upgrade existing SHARC source code.