This document is a technical note on using Analog Devices' DSP components and development tools, providing information on using Link Ports for point-to-point communication and discussing some tips and anomalies associated with the SHARC DSP family.
This Engineer-to-Engineer Note (EE-189) provides technical guidance on using Link Ports for point-to-point communication between Analog Devices SHARC DSPs. It covers the benefits of Link Ports, such as inter-processor communication and efficient data control, and details the specific hardware capabilities of the ADSP-2106x and ADSP-2116x families.
| ADSP-21060 & ADSP-21062 Link Ports | 6 Link ports, 4 bits wide, 1x or 2x core clock |
|---|---|
| ADSP-21160 Link Ports | 6 Link ports, 8 bits wide, up to 95 MHz |
| ADSP-21161 Link Ports | 2 Link ports, 8 bits wide, up to 100 MHz |
Link Ports enable point-to-point communication between DSPs, allow flexible data control via core or DMA, support bi-directional communication on a single link, and allow multiple simultaneous transfers.
They are memory-mapped, two-location deep FIFOs supporting 32 or 48-bit words. Reading an empty buffer or writing to a full buffer results in a core hang.
The workaround is to use 1x speed to avoid corrupted data caused by high operating temperatures and asynchronous CLKINs.