This Engineer-to-Engineer Note introduces the characteristics of the on-chip SDRAM controller found in the ADSP-TS20x TigerSHARC processor family. Although primarily based on the ADSP-TS201, it provides a list highlighting differences between derivatives such as the ADSP-TS202 and ADSP-TS203.
The document details the internal signal chain, address-mapping schemes, command truth tables for SDRAM execution, and power-up sequences. It also includes timing overviews, supported SDRAM device types, register descriptions (SYSCON, SDRCON), and optimization rules for performance.
| Maximum External Clock Frequency | 125 MHz |
|---|---|
| Processor Output FIFO Depth | six-stage |
| Maximum Addressable Rows (64-bit bus) | 8192 rows |
| Maximum Addressable Rows (32-bit bus) | 16384 rows |
| Supported SDRAM Voltage Levels | LVTTL (3.3V) and mobile low-power (2.5V) |
The document is based on the ADSP-TS201 but highlights differences for the ADSP-TS202 and ADSP-TS203.
No, neither Power-down nor Suspend modes are supported by this controller.