This Engineer-to-Engineer Note provides detailed technical information on the Analog Devices ADSP-TS101S TigerSHARC® On-chip SDRAM Controller
The document introduces the hardware-intensive solution of the on-chip SDRAM controller within the ADSP-TS101S TigerSHARC processor. It details how this component handles multiplexed row and column addressing, as well as refresh and precharge requirements for SDRAM systems.
Key sections cover the signal chain between the processor core and external memory, the internal architecture including command interfaces and FIFOs, supported SDRAM types, and specific command truth tables. The guide also provides programming instructions for registers like SYSCON and SDRCON, outlines the power-up sequence, and discusses DMA transfers and performance optimization techniques.
| Maximum External Clock Frequency | 100 MHz |
|---|---|
| Output FIFO Depth | 6 |
| Maximum Addressable Rows (64-bit bus) | 8192 rows |
| Maximum Addressable Rows (32-bit bus) | 16384 rows |
The external clock used for synchronous operation has a maximum frequency of 100 MHz.
No, although these are common SDRAM features, they are not supported by this specific controller.
The output FIFO has a depth of 6, which supports address pipelining for high-speed non-sequential read operations.