This document describes the multicycle instructions and latencies specific to the ADSP-BF531/532/533 Blackfin® Processor devices.
This document provides technical details on multicycle instructions that require more than one cycle to complete when executed from L1 memory. It covers categories such as Push Multiple, 32-bit Multiply, Call, Jump, Conditional Branch, and various synchronization operations, listing the specific cycle counts for each.
The guide also analyzes instruction latencies caused by dependencies between instruction pairs, including Accumulator to Data Register Latencies, Register Move Latencies, Loop Setup Latencies, Hardware Loop Latencies, Instruction Alignment Unit Empty Latencies, and L1 Data Memory Stalls. It explains how these conditions affect performance and offers strategies to avoid cycle penalties.
| Push Multiple/Pop Multiple cycles | # core cycles (where # is the number of registers) |
|---|---|
| 32-bit Multiply cycles | 3 cycles |
| Call and Jump cycles | 5 cycles (aligned target) |
| Return from Interrupt cycles | 5 cycles |
| Core Synchronization (CSYNC) cycles | 10 cycles |
The 32-bit by 32-bit integer multiply instruction always takes 3 cycles to complete.
All call and jump instructions take 5 cycles to complete, provided the target address is an aligned location.
Instruction latencies occur when a register is accessed in the instruction immediately following one that modifies it, or due to memory stalls and store buffer hazards.