This EE-Note describes how to achieve networking functionality with ADSP- BF536/ADSP-BF537 Blackfin® processors together with MII-compatible Ethernet Physical Layer Transceivers (PHYs) other than the SMSC LAN83C185, which is populated on the ADSP- BF537 EZ-KIT Lite® evaluation system.
This Engineer-to-Engineer Note describes the procedure for achieving networking functionality with ADSP-BF536/ADSP-BF537 Blackfin processors using MII-compatible Ethernet Physical Layer Transceivers (PHYs) other than the SMSC LAN83C185. The guide is based on the VisualDSP++ 4.5 development tool suite and its Ethernet MAC driver.
The document details the specific modifications required in the ADI_ETHER_BF537.c source code to accommodate different PHYs. Key changes involve updating the PHY address, clock settings, duplex capabilities, and auto-negotiation parameters. It also covers modifying the PHY ID check logic and interrupt handling routines to ensure compatibility with alternative devices like the SMSC LAN8187 or National Semiconductor DP83848.
The work was verified on an SMSC LAN8187 and on a National Semiconductor DP83848.
The procedure is based on the VisualDSP++ 4.5 development tool suite and its Ethernet MAC driver.
A modified version of ADI_ETHER_BF537.c is included in the .ZIP file associated with this EE-Note.