This document explains how to interface parallel ADCs to ADSP-21161 SHARC® processors. The parallel ADC considered in this application note is AD7865. This application note also provides example code to demonstrate how the SHARC processor’s external port can be programmed to receive data from the AD7865 in core and DMA modes.
This document is an Engineer-to-Engineer Note (EE-259) from Analog Devices that details the interfacing of the AD7865 parallel A/D converter with the ADSP-21161 SHARC processor. It covers the features of both components, including the 14-bit simultaneous sampling capabilities of the ADC and the SIMD architecture of the DSP.
| Resolution | 14-bit |
|---|---|
| Supply Voltage | 5 V |
| Power Consumption | 115 mW (typical) |
| Conversion Time | 2.4 us |
| Processor Speed | 100 MHz |
| Floating Point Performance | 600 MFLOPS |
Applications include AC motor control, uninterruptible power supplies, industrial power meters/monitors, and data acquisition systems.
The frame sync of SPORT0 is used to generate the /CONVST signal for the ADC.
The document provides example code demonstrating how the SHARC processor's external port can be programmed to receive data in core and DMA modes.