Analog Devices ADSP-21371 Power Dissipation Estimation EE-Note

About this manual

This document, titled "Estimating Power Dissipation for ADSP-21371 SHARC Processors" (EE-318), is a technical note contributed by Analog Devices engineers. It assists board designers in estimating power budgets and supply designs for the ADSP-21371 processor, which operates at core frequencies of 100-266 MHz.

The guide details how to calculate total power consumption by separating it into internal circuitry components (core and PLL) and external output drivers. It defines specific dynamic activity levels—Idle, Low, High, Peak, and Typical Peak—and provides scaling factors and formulas to estimate dynamic current based on application profiling.

What's inside

• Introduction
• Estimating Internal Power Consumption
• Internal Power Vector Definitions
• Dynamic Activity Levels (Table 1)
• Estimating Dynamic Current
• Activity Scaling Factors (Table 2)
• Calculating Total Dynamic Current
• Estimating Static Current

Specifications

Frequently asked questions

What are the defined dynamic activity levels for ADSP-21371?

The document defines five levels: Idle, Low, High, Peak, and Typical Peak.

Is the Peak activity level sustainable for normal applications?

No, the test code used to measure Ipp-INPEAK represents worst-case processor operation which is not sustainable under normal application conditions.