This document introduces system optimization techniques for Blackfin® processors, including external memory access latency optimization and system resource utilization optimization.
This document serves as a technical reference for utilizing the capabilities of Analog Devices Blackfin processors. It focuses on efficient system resource utilization to address bandwidth limitations caused by external memory access latencies. The note covers the processor's memory hierarchy, including L1 SRAM/Cache and L2 SRAM configurations.
| Maximum SDRAM frequency | 133 MHz |
|---|---|
| L2 access latency (Direct core instruction fetch) | 9 CCLKs |
| L2 access latency (Data fetch) | 11 CCLKs total |
Cache can be turned on using the Project Options dialog box or by defining the _cplb_ctrl constant.
L2 memory is available only on the ADSP-BF561 and ADSP-BF54x Blackfin processors.