The MC10E/100E452 is a 5-bit differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5V below VCC. The fully differential design of the device makes it ideal for very high frequency applications where a registered data path is necessary.
This datasheet describes the MC10E452 and MC100E452, which are 5-bit differential registers designed for very high frequency applications. The devices feature differential data inputs and outputs, as well as differential clock inputs, and are triggered by a positive transition of the positive clock input.
| Toggle Frequency (Min) | 1100 MHz |
|---|---|
| Package Type | 28-Lead PLCC |
| Supply Voltage Range (100E) | -4.2V to 5.46V |
| Maximum Toggle Frequency (Typ) | 1400 MHz |
| Propagation Delay to Output CLK (Diff) | 425 ps (Typ) |
A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW.
The registers are triggered by a positive transition of the positive clock (CLK) input.