This document describes the features and characteristics of the 74HC/HCT173 quad D-type flip-flop. It includes gated input enable for hold mode, gated output enable control, edge-triggered D-type register, asynchronous master reset, and output capability as a bus driver.
The Philips 74HC/HCT173 is a high-speed Si-gate CMOS device featuring a 4-bit parallel load register with clock enable control and master reset. It is pin compatible with low power Schottky TTL (LSTTL) and complies with JEDEC standard no. 7A.
The device includes gated input enable for hold mode, gated output enable control, and asynchronous master reset. The 3-state output buffers are controlled by a 2-input NOR gate, allowing the outputs to be placed in a high impedance OFF-state when required.
| Maximum clock frequency | 88 MHz |
|---|---|
| Input capacitance | 3.5 pF |
| Power dissipation capacitance | 20 pF per flip-flop |
It is a positive-edge triggered device.
The master reset is an active HIGH asynchronous input that clears all four flip-flops independently of other inputs.