The 74HC/HCT174 is a high-speed, low-power CMOS device that is pin compatible with low power Schottky TTL (LSTTL). The device features six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs simultaneously load and reset (clear) all flip-flops. The register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output of the flip-flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.
The Philips 74HC/HCT174 is a high-speed Si-gate CMOS device containing six edge-triggered D-type flip-flops with individual D inputs and Q outputs. It features a common clock (CP) and master reset (MR) input that load and reset all flip-flops simultaneously. The device is pin compatible with low power Schottky TTL (LSTTL) and is specified in compliance with JEDEC standard no. 7A.
| Number of flip-flops | Six |
|---|---|
| Trigger type | Positive-edge |
| Reset type | Asynchronous master reset |
| Propagation delay (CP to Qn) | 17 ns (typical) |
| Maximum clock frequency (HC) | 99 MHz |
| Maximum clock frequency (HCT) | 69 MHz |
| Supply voltage range (HC) | GND to Vcc |
| Supply voltage range (HCT) | GND to Vcc-1.5 V |
A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs.
The device is fully edge-triggered, transferring the D input state to the output on the LOW-to-HIGH clock transition.