M68AW127B 1Mbit (128K x8), 3.0V Asynchronous SRAM is a 3.0V asynchronous SRAM with low power consumption and low voltage data retention characteristics. It has 128K x 8 bits, low standby current and equal cycle and access times.
The M68AW127B is a 1Mbit CMOS SRAM organized as 131,072 words by 8 bits. It features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. The device requires a single 2.7 to 3.6V supply and includes an automatic power-down feature that reduces power consumption by over 99% when deselected.
The M68AW127B is available in SO32, TSOP32 8x20mm, and TSOP32 8x13.4mm packages. It supports read and write modes controlled by Chip Enable (E1), Chip Select (E2), and Write Enable (W) signals, with an Output Enable (G) signal for tri-state control.
| Capacity | 1Mbit (128K x 8 bits) |
|---|---|
| Supply Voltage | 2.7 to 3.6V |
| Access Time | 70ns |
| Low Vcc Data Retention | 1.5V |
| Operating Temperature | -55 to 125 °C |
| Storage Temperature | -65 to 150 °C |
| Output Current | 20 mA |
| Power Dissipation | 1 W |
The device requires a single supply voltage ranging from 2.7 to 3.6V.
No, the device features fully static operation requiring no external clocks or timing strobes.
The low Vcc data retention voltage is 1.5V.
The device is available in SO32, TSOP32 8x20mm, and TSOP32 8x13.4mm packages.