GS816018/32/36BT-250/200/150 is a high performance synchronous SRAM with a 2-bit burst address counter, developed by GSI Technology for Level 2 Cache applications supporting high performance CPUs. It is now widely used in synchronous SRAM applications, including DSP main store and networking chip set support. The device has a 2.5 V or 3.3 V +10%/–10% core power supply, a 2.5 V or 3.3 V I/O power supply, Byte Write (BW) and/or Global Write (GW) operation, internal self-timed write cycle and automatic power-down function.
The GS816018/32/36BT is a high‑performance synchronous burst SRAM available in 1M × 18, 512K × 32 and 512K × 36 configurations. It supports 2.5 V or 3.3 V core supplies, offers flow‑through or pipeline read modes, byte‑write and global‑write functions, and a low‑power sleep mode.
The device is supplied in a JEDEC‑standard 100‑pin TQFP package (RoHS‑compliant) with speed grades of 250 MHz, 200 MHz and 150 MHz. Detailed pin descriptions, register maps, burst counter sequences and ordering information are provided for designers.
| Core voltage | 2.5 V or 3.3 V |
|---|---|
| Package type | 100‑pin TQFP (RoHS‑compliant) |
| Maximum operating frequency | 250 MHz, 200 MHz, 150 MHz |
| Memory density options | 1M × 18, 512K × 32, 512K × 36 |
It operates on a 2.5 V or 3.3 V core supply, and all inputs are compatible with both voltages.
The device is offered in a 100‑pin TQFP package that is RoHS‑compliant.
It is available in speed grades of 250 MHz, 200 MHz and 150 MHz.