The Hitachi HM51(S)4260C is a CMOS dynamic RAM organized as 262,144-word × 16-bit. It has achieved higher density, higher performance, and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a high-speed access mode. Multiplexed address input allows the HM51(S)4260C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. The internal refresh timer enables HM51S4260C self-refresh operation.
The HM514260C/HM51S4260C series are high‑density, high‑performance CMOS dynamic RAMs fabricated with a 0.8 µm process. They are offered in standard 400‑mil 40‑pin SOJ and 44‑pin TSOP‑II packages and support fast page mode operation.
Key features include single‑5 V operation, low power dissipation, multiple refresh options, and a variety of access times (60 ns, 70 ns, 80 ns). The datasheet provides full pin descriptions, timing diagrams, absolute maximum ratings, DC characteristics, and package dimensions for designers.
| Memory capacity | 262,144‑word × 16‑bit |
|---|---|
| Access time | 60 ns / 70 ns / 80 ns (max) |
| Power dissipation | 1.0 W |
The devices are offered in standard 400‑mil 40‑pin plastic SOJ and standard 400‑mil 44‑pin plastic TSOP‑II packages.
Standby mode power consumption is 11 mW (max) for the HM51(S)4260C‑6/7/8 versions.