PSD935G2 is a configurable memory system on a chip for 8-bit microcontrollers. It features 5 V±10% single supply voltage, 4 Mbit of primary flash memory, 256Kbit of secondary flash memory, 64 Kbit of SRAM, over 3,000 gates of PLD, 52 reconfigurable I/O ports, enhanced JTAG serial port, programmable power management, and high endurance.
The PSD935G2 is a configurable memory system on a chip (SoC) designed for 8‑bit microcontrollers. It integrates up to 4 Mbit of primary Flash, 256 Kbit secondary Flash, 64 Kbit SRAM, more than 3 000 PLD gates and 52 reconfigurable I/O ports, all powered from a single 5 V supply. The device supports both JTAG‑based In‑System Programming (ISP) and In‑Application Re‑Programming (IAP) for flexible firmware updates.
The architecture includes a Decode PLD for address decoding, a General‑Purpose PLD for custom logic, a built‑in JTAG serial port, an internal page register for address expansion, and a Power Management Unit with an automatic power‑down mode. Pin‑level details, programming methods, and ordering information are provided throughout the document.
| Primary Flash Memory | 4 Mbit |
|---|---|
| Secondary Flash Memory | 256 Kbit |
| SRAM | 64 Kbit |
| PLD Gate Count | >3 000 gates |
| Reconfigurable I/O Ports | 52 pins |
| Supply Voltage | 5 V ±10 % |
| Standby Current | 50 µA (typical) |
| PLD Erase/Write Cycles | ≥1 000 |
| Package | 80‑pin TQFP |
It includes a built‑in JTAG‑compliant serial port that allows full‑chip In‑System Programming (ISP) via the JTAG pins on Port E.
The main Flash can be programmed in‑system by the MCU while it runs code from the secondary Flash or SRAM, allowing concurrent operation and firmware updates.