Altera SignalTap II Logic Analyzer is a tool that helps to debug designs. It allows you to examine the behavior of internal signals without using extra I/O pins, while the design is running at full speed on an FPGA device.
The document describes the SignalTap II Logic Analyzer, a system-level debugging tool that captures and displays real-time signal behavior in SOPC or FPGA designs without requiring external I/O pins. It allows users to examine internal signals while the design runs at full speed on an Altera device.
The guide covers the complete workflow for using the logic analyzer, including adding it to a project, configuring instances, defining triggers, compiling the design, programming the target device, running the analysis, and viewing captured data. It also details features such as incremental compilation, multiple clock domain support, and MATLAB integration.
| Max channels per instance | Up to 2,048 |
|---|---|
| Max samples per device | 128K |
| Trigger conditions | Up to 10 basic or advanced |
No, it does not require external probes or changes to design files to capture internal nodes.
It helps debug an FPGA design by probing the state of internal signals without using extra I/O pins or external equipment.
Up to 2,048 channels per logic analyzer instance.
Up to 128K samples in each device.