Altera IP Compiler for PCI Express User Guide

About this manual

The document serves as a comprehensive user manual for the Altera IP Compiler for PCI Express. It details the setup of the IP core within Quartus II projects using both SOPC Builder and Qsys flows, covering parameterization, simulation, and compilation steps.

The guide provides in-depth technical information on the IP core architecture, including interfaces (Avalon-ST, Avalon-MM), register descriptions for configuration space, reset and clock requirements, and transaction layer protocol details. It also includes specific sections on optional features like ECRC and ASPM, error handling, external PHY support, and debugging hardware bring-up issues.

What's inside

• Datasheet Features
• Getting Started
• Parameter Settings
• IP Core Architecture
• Register Descriptions
• Reset and Clocks
• Transaction Layer Protocol
• Optional Features
• Interrupts
• Testbench and Design Example

Specifications

Frequently asked questions

What clock frequencies are required for the Avalon-MM interface?

The manual specifies that a 100 MHz reference clock and either a 125 MHz or 250 MHz application clock are used.

What external PHY modes does the IP Compiler support?

The document lists support for 16-bit SDR, 8-bit DDR, and 8-bit SDR modes for external PHYs.