Update: 01 October, 2023
The product is a 5-tap silicon delay line that provides 5 equally spaced taps with delays ranging from 12ns to 250ns, with an accuracy of ±2ns or ±3%, whichever is greater. This product is offered in a standard 14-pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin SOICs are also available. Through the combination of a 100% silicon delay line and industry standard DIP and SOIC packaging, both enhanced performance and superior reliability over hybrid technology are achieved. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead configurations. The product reproduces the input logic level at each tap after the fixed delay specified by the dash number in Table 1. The product is designed with both leading and trailing edge accuracy. Each tap is capable of driving 10μA of load. The operating voltage of the product is ±5V. The product operates stably and reliably in the temperature range of -40~85℃.
File format: PDF
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MD5 Checksum: AC0B9AD6D07DA5F1B5AE2855FD14EA77
Publication date: 11 May, 2012
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PDF Link: DALLAS semiconductor DS1005 5-Tap Silicon Delay Line Manual PDF