DS1020 Programmable 8-Bit Silicon Delay Line
The DS1020 programmable 8‑bit silicon delay line provides precise timing adjustments via either a 3‑wire serial interface or an 8‑bit parallel port. It is offered in standard 16‑pin DIP and 16‑pin SOIC packages and is TTL/CMOS compatible, capable of driving 10 LS‑type loads.
The device includes detailed electrical specifications, timing diagrams for both parallel and serial modes, and guidelines for cascading multiple units in a daisy‑chain configuration. Test conditions, absolute maximum ratings, and electrical characteristics are fully documented for design integration.
| Maximum delay (fastest model) | 48.25 ns |
|---|---|
| Maximum delay (slowest model) | 520 ns |
| Delay step sizes | 0.15 ns, 0.25 ns, 0.5 ns, 1 ns, 2 ns |
| Supply voltage VCC | 5.0 V (typ) |
| Operating temperature range | 0 °C to 70 °C |
| Short‑circuit output current | 50 mA (1 s) |
| Clock frequency | 10 MHz |
By daisy‑chaining their serial ports, connecting the Q output of one device to the D input of the next.
The enable pin (E) must be held at logic 1 while loading or reading the internal 8‑bit register.