This document introduces the features and characteristics of DS1005 5-Tap Silicon Delay Line, including the structure, function and application scenarios.
The DS1005 5‑Tap Silicon Delay Line from Dallas Semiconductor offers five equally spaced taps with selectable delays ranging from 12 ns to 250 ns. It is available in 14‑pin DIP, 8‑pin DIP, and 16‑pin SOIC packages and is TTL/CMOS compatible.
The document lists pin assignments, absolute maximum ratings, DC and AC electrical characteristics, timing diagrams, and test setup procedures. It also includes a delay table for standard part numbers and notes on temperature and voltage effects on delay accuracy.
| Number of taps | 5 |
|---|---|
| Delay range | 12 ns to 250 ns |
| Supply voltage (Vcc) | 4.75 V to 5.25 V |
| High‑level input voltage | 2.2 Vcc + 0.5 V |
| Low‑level input voltage | -0.5 V to 0.8 V |
| Active current | 40 mA to 70 mA |
| High‑level output current | -1.0 mA |
| Low‑level output current | 12 mA |
| Input capacitance | 5 pF to 10 pF |
The DS1005 provides delays from 12 ns up to 250 ns.
It has five equally spaced taps.
The device operates with a supply voltage between 4.75 V and 5.25 V.