CYPRESS Delta39K ISR CPLD Family CPLDs at FPGA Densities handbook

Update: 30 September, 2023

This document introduces the features of the Cypress Delta39K ISR CPLD Family products, including high density, high speed, multiple voltage interfaces, low power consumption, and simple timing model.


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MD5 Checksum: 60461DA76725C458F2FDA84FE4DF7F9B

Publication date: 10 May, 2012

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PDF Link: CYPRESS Delta39K ISR CPLD Family CPLDs at FPGA Densities handbook PDF

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