This document introduces the features of the Cypress Delta39K ISR CPLD Family products, including high density, high speed, multiple voltage interfaces, low power consumption, and simple timing model.
The Delta39K ISR CPLD family from Cypress provides high‑density programmable logic with up to 200 K usable gates, extensive I/O options, and low‑power operation. Devices support AnyVolt™ I/O ranging from 1.5 V to 3.3 V and include embedded SRAM, channel memory, and cluster memory.
The architecture is built around Logic Block Clusters with programmable inter‑connect matrices, four global clocks, and flexible clock‑polarity control. JTAG‑compliant in‑system reprogrammability (ISR) and boundary‑scan features enable design changes without hardware modifications.
| Usable gates | 30 K to 200 K |
|---|---|
| Macrocells | 512 to 3072 |
| Maximum I/O pins | 136 to 428 |
| In‑system speed | 233 MHz |
| Standby current | as low as 5 mA |
| Embedded SRAM | 80 K to 480 K bits |
| Channel memory | 16 K to 96 K bits (dual‑port) |
| Supported I/O voltages | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
The devices operate up to 233 MHz in‑system.
Depending on the density, the family supports between 136 and 428 I/O pins.
The AnyVolt™ interface allows 1.5 V, 1.8 V, 2.5 V, and 3.3 V I/O levels.