This document is an introduction to the features and characteristics of AS7C33128PFS32B AS7C33128PFS36B 3.3V 128K X 32/36 pipeline burst synchronous SRAM
The AS7C33128PFS32B and AS7C33128PFS36B are 4‑Mbit CMOS synchronous SRAMs organized as 131,072 words × 32 or 36 bits. They feature a two‑stage register‑to‑register pipeline, fast clock speeds up to 200 MHz, and support both interleaved and linear burst modes.
The devices operate from a 3.3 V core supply with optional 2.5 V I/O, are offered in a 100‑pin TQFP package, and include multiple chip‑enable inputs for easy expansion. Detailed timing, pin‑out, and electrical specifications are provided for system designers.
| Organization | 131,072 words × 32 or 36 bits |
|---|---|
| Maximum clock frequency | 200 MHz (166 MHz, 133 MHz options) |
| Clock‑to‑data access time | 3.0 ns / 3.5 ns / 4.0 ns |
| OE access time | 3.0 ns / 3.5 ns / 4.0 ns |
| Core power supply | 3.3 V |
| I/O supply voltage | 2.5 V or 3.3 V |
| Package | 100‑pin TQFP (14 mm × 20 mm) |
| Maximum operating current | 375 mA (200 MHz), 350 mA (166 MHz), 325 mA (133 MHz) |
| Maximum standby current | 130 mA (200 MHz), 100 mA (166 MHz), 90 mA (133 MHz) |
The core power supply voltage is 3.3 V.
The devices support up to 200 MHz (with lower options of 166 MHz and 133 MHz).
They are available in a 100‑pin TQFP package measuring 14 mm × 20 mm.
I/O pins operate at either 2.5 V or 3.3 V, depending on the selected V/O supply.