This document is the specification of AS4C4M4F0 AS4C4M4F1 5V 4M×4 CMOS DRAM (Fast Page mode). It mainly introduces the features and characteristics of this product, including organization, speed, power consumption, refresh, package, pin arrangement, pin definition and selection guide.
This document is a technical datasheet for the AS4C4M4F0 and AS4C4M4F1, which are high-performance 16-megabit (4,194,304 words x 4 bits) CMOS Dynamic Random Access Memory (DRAM) devices. These chips feature fast page mode operation and are designed for use as main memory in PC, workstation, router, and switch applications.
| Organization | 4,194,304 words x 4 bits |
|---|---|
| RAS access time (50ns) | 50 ns |
| CAS access time (50ns) | 12 ns |
| Active power consumption | 908 mW max |
| Standby power consumption | 5.5 mW max |
| Operating voltage (Vcc) | 4.5 to 5.5 V |
| Package types | 24/26-pin SOJ, TSOP |
The AS4C4M4F0 requires a refresh interval of 64 ms.
The AS4C4M4F1 requires a refresh interval of 32 ms.