This document introduces the features and characteristics of the QED RM5271 microprocessor. It is a dual-issue superscalar microprocessor that can issue one integer instruction and one floating-point instruction per cycle.
The ACT5271 is a highly integrated 64‑bit superscalar microprocessor that implements a superset of the MIPS IV ISA. It can issue an integer and a floating‑point instruction in the same cycle and includes a 32 KB instruction cache, a 32 KB data cache, a 48‑entry fully associative TLB and a high‑performance floating‑point unit capable of up to 532 MFLOPS.
The device is offered in several packages, including a 208‑lead CQFP (F17) and a 179‑pin PGA (P10). Detailed pin‑out tables, package dimensions and ordering part numbers are provided, along with operating frequency options of 150 MHz, 200 MHz and 250 MHz and power consumption of about 4.2 W at 200 MHz.
| Operating frequency | 150 MHz, 200 MHz, 250 MHz |
|---|---|
| Dhrystone performance | 345 MIPS |
| SPECint95 | 7.3 |
| Floating‑point performance | up to 532 MFLOPS |
| Typical power consumption | 4.2 W @ 200 MHz |
| Core voltage | 2.5 V core, 3.3 V I/O |
| Instruction cache size | 32 KB, 2‑way set associative |
| TLB entries | 48 dual entries (96 pages) |
The ACT5271 is offered at 150 MHz, 200 MHz and 250 MHz.
Typical power consumption is about 4.2 W at 200 MHz.
The core operates at 2.5 V with 3.3 V I/O pins.