The CY7C1386D/CY7C1387D SRAM is a high-performance 18-Mbit synchronous static random access memory with features such as scalability, double-cycle deselect, and fast access speed.
The CY7C1386D and CY7C1387D are high‑performance synchronous SRAMs offering 512 K × 36‑bit and 1 M × 18‑bit configurations. They support bus operation up to 250 MHz, provide selectable burst modes (linear or interleaved), and feature double‑cycle deselect for fast depth expansion.
The devices operate from a +3.3 V core supply with 2.5 V/3.3 V I/O options, and are available in 100‑pin TQFP, 119‑ball BGA, and 165‑ball fBGA packages. Pin definitions, timing diagrams, and functional block diagrams are included for design integration.
| Maximum Access Time | 2.6 ns (250 MHz), 3.0 ns (200 MHz), 3.4 ns (167 MHz) |
|---|---|
| Maximum Operating Current | 350 mA (250 MHz), 300 mA (200 MHz), 275 mA (167 MHz) |
| Maximum CMOS Standby Current | 70 mA (all speed grades) |
| Core Supply Voltage | +3.3 V |
| I/O Supply Voltage | 2.5 V or 3.3 V |
| Package Options | 100‑pin TQFP, 119‑ball BGA, 165‑ball fBGA |
The maximum access time is 2.6 ns for the 250 MHz speed grade.
It uses a +3.3 V core supply and supports 2.5 V or 3.3 V I/O operation.
The devices are offered in 100‑pin TQFP, 119‑ball BGA, and 165‑ball fBGA packages.
The ZZ pin is a sleep input; when asserted HIGH it places the device in a low‑power sleep condition.