The Cypress UltraLogic™ 128-Macrocell Flash CPLD, model CY7C374i, is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) that features 128 macrocells, 64 I/O pins, 5 dedicated inputs including 4 clock pins, In-System Reprogrammable (ISR™) Flash technology, JTAG interface, Bus Hold capability, no hidden delays, high speed, fully PCI compliant, 3.3V or 5.0V I/O operation. Available in 84-pin PLCC, 84-pin CLCC, and 100-pin TQFP packages, and pin compatible with the CY7C373i.
The CY7C374i is an UltraLogic™ 128‑macrocell flash CPLD from Cypress, offering In‑System Reprogrammable (ISR) flash technology via a JTAG interface. It provides 64 I/O pins, 5 dedicated inputs (including 4 clock pins), bus‑hold capabilities, and full PCI Local Bus compliance.
The device is available in 84‑pin PLCC, 84‑pin CLCC, and 100‑pin TQFP packages. It supports both 3.3 V and 5.0 V I/O operation, features a simple timing model with no hidden delays, and includes design‑tool support from Cypress Warp2/3 as well as third‑party EDA tools.
| Maximum fmax | 125 MHz |
|---|---|
| Propagation delay (tpp) | 10 ns |
| Typical supply current | 125 mA |
| Input capacitance (Vin = 5 V, f=1 MHz) | 8 pF |
| Maximum reprogramming cycles | 100 cycles |
| I/O voltage options | 3.3 V or 5.0 V |
| Number of I/O pins | 64 |
The device can operate up to 125 MHz fmax.
It provides 64 I/O pins.
The CPLD can operate with either 3.3 V or 5.0 V I/O voltage.
The device is rated for a minimum of 100 reprogramming cycles.