This datasheet introduces the features of 1:20 Differential Clock/Data Fanout Buffer FastEdge™ Series CY2DP3120.
The CY2DP3120 is a low‑skew, low‑propagation‑delay 1‑to‑20 differential fanout buffer designed for high‑performance clock and data distribution. It provides twenty ECL/PECL differential outputs, selectable clock inputs, and can translate ECL/PECL signals while maintaining sub‑picosecond jitter.
The device is supplied in a 52‑lead 1.4 mm TQFP package, operates from –40 °C to 85 °C, and supports both PECL and ECL supply ranges. Ordering information includes tape‑and‑reel and lead‑free options. Detailed electrical specifications, pin definitions, and test configurations are provided throughout the document.
| Differential outputs | Twenty ECL/PECL differential outputs |
|---|---|
| Clock inputs (ECL/PECL) | One ECL/PECL compatible differential or single-ended clock inputs |
| Clock inputs (HSTL) | One HSTL compatible differential or single-ended clock inputs |
| Output‑to‑output skew | 50 ps |
| Device‑to‑device skew | 150 ps |
| Propagation delay (typical) | 500 ps |
| Period jitter (max) | 1.4 ps RMS |
| Maximum operating frequency | 1.5 GHz (2.7 GHz max toggle) |
| PECL mode supply range | 2.5 V ±5% to 3.3 V ±5% (VEE = 0 V) |
| ECL mode supply range | -2.5 V ±5% to -3.3 V ±5% (VEE = 0 V) |
| Operating temperature range | -40 °C to 85 °C |
| Package | 52‑pin 1.4‑mm TQFP |
The device provides a 50 ps output‑to‑output skew.
PECL mode operates from 2.5 V ±5% to 3.3 V ±5% with VEE tied to 0 V.
It is rated for industrial temperatures from –40 °C to 85 °C.
The device offers twenty ECL/PECL differential outputs.