The MAX3882A is a 2.488Gbps 1:4 demultiplexer with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps serial data to 4-bit-wide, 622Mbps parallel data for SDH/SONET applications
The MAX3882A is a 2.488 Gbps serial data deserializer with an integrated limiting amplifier, PLL, and 4‑bit LVDS parallel output. It operates from a single +3.3 V supply, consumes 610 mW, and does not require an external reference clock.
The document includes absolute maximum ratings, DC and AC electrical characteristics, pin functions, detailed functional description, design guidelines, a typical application circuit, and package information for the 36‑pin TQFN package.
| Serial Input Rate | 2.488 Gbps |
|---|---|
| Parallel Output Rate | 622 Mbps |
| Supply Voltage | +3.3 V |
| Power Dissipation | 610 mW |
| Operating Temperature Range | -40 °C to +85 °C |
| Differential Input Range | 10 mVp‑p to 1.6 Vp‑p |
| LVDS Output High Voltage (VoH) | 1.475 V |
| LVDS Output Low Voltage (VoL) | 0.925 V |
| Package Type | 36‑pin TQFN (6 mm × 6 mm) |
No, the device does not require an external reference clock for data acquisition.
The LOL output is LVTTL and active low.
The part is supplied in a 36‑pin TQFN‑EP package (code T3666‑2).