The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V35761/81 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is enabled, each additional cycle will provide data on the subsequent two rising clock edges.
The IDT 71V35761S is a high‑speed 3.3 V synchronous SRAM available in 128K × 36 and 256K × 18 configurations. It supports commercial speeds up to 200 MHz (3.1 ns access) and industrial speeds up to 166 MHz (3.5 ns access), with burst mode and pipelined outputs.
The device includes a full pin description, optional JTAG interface, and is offered in 100‑pin TQFP, 119‑pin BGA, and 165‑pin fine‑pitch BGA packages. Absolute maximum ratings, recommended operating temperatures, and electrical characteristics are detailed for both commercial (0 °C to +70 °C) and industrial (‑40 °C to +85 °C) use.
| Memory configurations | 128K × 36, 256K × 18 |
|---|---|
| Core supply voltage (Vpp) | 3.135 V – 3.465 V |
| Clock access time (200 MHz) | 3.1 ns |
| Clock access time (183 MHz) | 3.3 ns |
| Clock access time (166 MHz) | 3.5 ns |
| Commercial temperature range | 0 °C to +70 °C |
| Industrial temperature range | ‑40 °C to +85 °C |
The device is offered in 128K × 36 and 256K × 18 SRAM configurations.
The core supply voltage (Vpp) operates between 3.135 V and 3.465 V.
Commercial use is from 0 °C to +70 °C, while industrial use is from ‑40 °C to +85 °C.