IDT72511 and IDT72521 are highly integrated first-in, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. Port B is also 18 bits wide and can be connected to another processor or peripheral.
The IDT BiFIFO family provides two side‑by‑side FIFO memory arrays for bidirectional data transfers. The devices support 18‑bit or 36‑bit bus configurations and include programmable flags, bypass paths, and DMA control pins.
The handbook details pin assignments, command registers, reset procedures, and timing diagrams, and includes ordering information such as package types and temperature ranges for both commercial and military use.
| FIFO depth (IDT72511) | 512 x 18 bits |
|---|---|
| FIFO depth (IDT72521) | 1024 x 18 bits |
| Access time | 35 ns |
| Package types | 68‑pin PGA, 68‑pin PLCC |
| Military temperature range | -55 °C to +125 °C |
Each FIFO provides two programmable flags, Almost‑Empty and Almost‑Full, which can be assigned to external flag pins.
The device includes six general‑purpose programmable I/O pins.
A hardware reset is triggered via the RS pin when specific pin conditions are met, resetting all BiFIFO functions.