IDT72V72x0 is a high-density high-speed synchronous FIFO from IDT
The IDT72V series are 3.3 V high‑density Supersync II FIFO devices offering configurable memory depths from 512 × 72 bits up to 65,536 × 72 bits. They support bus‑matching widths of 72, 36 or 18 bits on both input and output ports and provide selectable big‑endian or little‑endian word formats.
The datasheet describes the functional block diagram, pin configuration, programmable flag features, timing modes (IDT Standard and First‑Word‑Fall‑Through), JTAG boundary‑scan support, and power‑down behavior. Electrical ratings, absolute maximum limits, and recommended operating conditions are also listed.
| Supply Voltage | 3.15 V – 3.45 V |
|---|---|
| Operating Temperature Range | -55 °C to +125 °C |
| Maximum Clock Frequency | 100 MHz (10 ns read/write cycle) |
| Package | 256‑pin Fine Pitch BGA (PBGA) |
| Bus‑Matching Widths | x72, x36, x18 |
The devices support input and output bus widths of 72, 36, or 18 bits, selectable via the IW, OW, and BM pins.
Yes, the FIFO automatically powers down when idle to minimize standby current, and any control input will wake it.