This document provides the version history and revision details for 128Mb DDR SDRAM DDR SDRAM specification. It describes the features and performance of DDR SDRAM.
The handbook provides a complete description of Samsung's 128Mb DDR SDRAM, covering revision history, key features, package pinout, and functional operation. It includes state diagrams, command sequences, and timing diagrams for read, write, auto‑precharge, refresh, and power‑down modes.
Electrical characteristics are given in detail, with DC operating conditions, AC timing parameters, input/output capacitance, and IBIS I/V characteristics. The document also lists absolute maximum ratings, QFC function details, and package dimensions for the TSOP2 form factor.
| Operating frequency (CL=2) | 133MHz |
|---|---|
| Operating frequency (CL=2.5) | 133MHz |
| Package type | TSOP2 (400mil x 875mil) |
| Input capacitance | 2.0pF ~ 3.0pF |
| Maximum Vih | 4.2V (overshoot < 3ns) |
| tRAS timing | 45ns at 133MHz/CL2.5 |
The maximum Vih is 4.2 V, and any overshoot voltage lasts less than 3 ns at VDD.
It uses a TSOP2 package measuring 400 mil by 875 mil.
The input capacitance is specified as 2.0 pF to 3.0 pF with a ΔC_in of 0.25 pF.
The device supports 133 MHz with CL = 2, 133 MHz with CL = 2.5, and 100 MHz with CL = 2.